The pressure to reduce the
manufacturing cost of TFT LCD displays is as constant and intense as it is
in the semiconductor industry. To increase productivity, IC makers continuously
reduce the sizes of c-Si chips and transistors in order to increase the number
of chips per wafer.
IC makers increase
productivity by continuously reducing chip size and
increasing wafer size to increase the number of chips per wafer.
But this strategy doesn't
work for LCDs because the panel sizes users demand most get steadily larger,
Still, by increasing the number of panels produced on a single substrate,
the cost of TFT-array processes can be reduced.
The IC makers' size-reduction
strategy doesn't work for direct-view LCDs, but
LCD manufacturers can still reduce the cost of TFT-array processes by
increasing the number of panels produced on a single substrate.
This process requires that
the size of the glass substrate be steadily increased so that the number of
LCD panels fabricated upon it can increase.
For more panels to be put on a glass substrate, the substrate size must be
steadily increased - which requires the continual design and construction
new generations of process equipment.
New generations of process
equipment must be continually designed and built to achieve these increases.
The fabrication processes this equipment must implement will be described
We can assume that the display being fabricated is a color TFT LCD that uses
an inverse-staggered-type a-Si TFT as the active-matrix switching element.
Fabricating the TFT
The manufacturing process
used to fabricate an a-Si TFT array is very similar to those used to fabricate
c-Si semiconductor devices. The various steps, including cleaning, deposition
of thin films, photolithography, and wet and dry etching of the thin films
- are alsso very similar. The difference between the a-Si TFT process and
the c-Si semiconductor process is that a semiconductor layer is deposited
onto a glass substrate in the a-Si TFT process, while Si wafers are used as
the substrate in the c-Si semiconductor process. Today, critical issues in
the processing of TFT arrays include the development of a low-resistance gate-bus
line, uniform and fine etching, and improved lithographic accuracy.
TFT-array technologies are aimed at achieving high precision, large aperture
ratio, and low power consumption, in addition to large screen size.
AMLCD manufacturers are also competing to minimize the number of array processes
by reducing the number of photo masks and simplifying the thin-film-formation
and etching processes.
In the bottom-gate TFT-array
fabrication process, the first layer consists of the gate electrodes and gate
bus-lines, which can have one or two metal layers.
Some storage capacitors can be constructed by using a part of the gate electrode
as an electrode of the storage capacitor - which is called the Cs-on-gate
method - while other capacitors are constructed independent of a gate bus-line.
If the independent Cs lines
are constructed simultaneously with the gate bus-lines using the same metal
layer, there is no difference in the fabrication process between the Cs-on-gate
method and the independent Cs bus-line method.
The processing of an a-Si TFT array is complex.
This flowchart outlines
the processes for making an a-Si TFT array using a
bottom-gate TFT structure and an independent storage capacitor.
After constructing gate
and storage-capacitor electrodes with 2000-3000A of a metal such as aluminum,
chromium, tantalum, or tungsten, a triple layer of silicon nitride and amorphous
silicon is deposited by using plasma-enhanced chemical-vapor deposition (PECVD).
In the etch-back type of
TFT structure, the triple layer consists of 4000A of SiNx, 2000A of a-Si,
and 500 A OF n+a-si, which is deposited over the gate electrode in a continuous
process, i.e., a process without a vacuum break.
For the etch-stopper type
of TFT structure, 4000A of SiNx, 500A OF a-Si, and 2000A of n+a-si are deposited.
Let us look at the etch-back TFT fabrication process in more detail.
After defining the a-Si
area by using photolithography and plasma dry etching, an ITO layer is deposited
with a thickness of about 500A via sputtering.
Then, the pixel electrodes
are patterned. About 2000A of metal is sputter deposited, while data bus-lines
and TFT electrodes are patterned by photolithography.
Then the ohmic contact layer
(n+a-Si) at the channel region is etched by dry etching using the source and
drain electrodes as an etch-protect mask.
Finally, a protective 2500A SiNx layer is deposited by PECVD and contact windows
The etch-stopper TFT structure
requires one more process step - a chemical vapor deposition (CVD) - than
does the etch-back TFT structure.
For etch-stopper TFT fabrication, a n+a-Si layer is deposited separately after
the top insulator of triple-layer (SiNx/a-Si/SiNx) is patterned.
The a-Si area is patterned
and the n+a-Si layer at the top of etch-stopper is removed. The source and
drain electrodes are formed using about 2000A of metal; then, about 500A of
ITO is sputter deposited, and pixel electrodes are patterned.
A SiNx protective layer is then deposited by PECVD and, finally, the contact
windows are opened.
Fabricating Color Filters
Color filters (CFs) can
be made with either dyes or pigments, utilizing coloring method such as dyeing,
diffusion, electro-deposition, and printing.
Color filters (CFs)
can be made with either dyes or pigments, and can be
further divided by coloring method.
There are several fairly
common color-element configurations for LCDs.
Stripe is the most popular, followed by mosaic and delta.
Among the many combinations
of configuration and types of CF fabrication methods, the color-resist method
with stripe-type RGB arrangement is currently the most popular.
Between the blocks of color
in the CF is a black matrix (BM) made of an opaque metal, such as chromium,
which shields the a-Si TFTs from stray light and prevents light leakage between
A double layer of Cr and CrOx is used to minimize reflection from the BM.
The sputter-deposited BM film is patterned using photolithography.
For reduced cost and reflectivity,
black resin made by diffusing C and Ti in photo resist - can be used as a
In the color-resist method, the primary color-filter patterns are formed by
using a photolithography technique.
The color-resist is negative
and made by diffusing pigment in a UV-curing resin, such as an acryl-epoxy
resin, and by dissolving the resin in a solvent.
A red colored resist is spin-coated onto a glass substrate on which a BM has
previously been formed.
The red pattern is then formed by exposing the red resist through a mask and
The process is repeated
using the same mask with a shifted mask-align technique for green- and blue-colored
A protective film is then applied, and 1500A of ITO for the TFT array's common
electrode is sputter-deposited to finish the color filter.
Liquid-crystal Cell Process
The TFT-array and color-filter
substrates are made into an LCD panel by assembling the two substrates together
with a sealant, while the cell gap is maintained by spacers.
The TFT-array and
color-filter substrates are made into an LCD panel by
assembling them with a sealant.
The assembly is begun by
printing a polyimide alignment film on a cleaned TFT-array, and then rubbing
the surface of the film with a piece of cloth wound on a roller, which orients
the polyimide molecules in one direction.
Similarly, alignment film
is applied to the color-filter substrate, and this substrate is also rubbed.
After the rubbing process, a sealant is applied to the periphery of the TFT-array
substrate. To form electrical connections from the common electrodes on the
color-filter substrate to the TFT array, the TFT-array substrate is coated
with a conducting paste around the periphery.
At the same time, spacers
to control the cell gap are sprayed onto the color-filter substrate. (In some
cases, spacers are sprayed on to the TFT-array substrate, and a sealant is
applied to the color-filter substrate.)
The two substrates are then assembled after the sealant is pre-hardened.
The sealant is then hardened completely with heat and pressure.
Then, the assembled substrates
are scribed using a diamond wheel and separated into individual cells, and
the empty cells are filled with liquid crystal material by vacuum injection.
Finally, a sealing agent
is used to seal the cell, and the polarizers are applied to both cell surfaces
after a visual function test.
Assembling LCD Modules
Although critical for producing
panels with the desired characteristics and price, the details of the manufacturing
process for AMLCD panels are often of less immediate interest to the OEM purchasers
of displays than are the details of the module assembly process.
This is so because it is
the physical and electrical characteristics of the module that OEMs must deal
with when integrating the display into products for end users.
The process flow for assembling
a module using the tape-automated-bonding (TAB) method is conceptually straightforward,
but it's not simple.
The process for assembling
LCD modules(flow chart).
The first decision to make
is whether you want to use TAB at all, or whether you would prefer the other
basic way of applying the LDI chips needed to drive the TFT panel.
In the TAB method, the LDI
chip is attached to a tape-carrier package (TCP), and the TCPs are then connected
to the TFT-array substrate.
The structure of the tape-carrier package used in TAB.
Anisotropic conducting film
(ACF) is applied to the contact pads, where the stripe-shaped contact leads
are formed as a group. The TCPs are then aligned and subjected to pressure-bonding.
The drive-circuit components, such as the timing controller, EMI filters,
op amps, chip capacitors, and resistors, are mounted onto a multi-layered
PCB using a surface-mount technology (SMT).
A soldering method is usually employed to connect the gate and control PCBs
to the other end of the TCP leads, but in some cases ACF bonding can be used
Mounting a TAB using
a TCP and ACF.
Sometimes, to minimize bezel
size, the drive-circuit unit is set to the back side of the LCD module by
using bent TCPs.
Alternatively, one can use
the chip-on-glass (COG) method, in which LDI chips are mounted directly on
the TFT-array substrate.
The choice of COG or TAB
is determined by the peripheral area available and the limitations on bezel
size for the display.
After testing the electrical
functions, only the good LCD panels are subjected to the final assembly process,
in which a backlight unit and a metal bezel are attached to compete the LCD
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